Liquid crystal display panel device with a transparent conductive film formed pixel electrode and gate pad and data pad on substrate and method of fabricating the same

ABSTRACT

A liquid crystal display panel device includes a thin film transistor array substrate having a gate line provided on a substrate, a data line intersecting the gate line and having a gate insulating pattern disposed therebetween to define a pixel area, a thin film transistor provided at the intersection between the gate line and the data line, a protective film for protecting the thin film transistor, a pixel electrode provided at the pixel area and connected to the thin film transistor, a gate pad connected to the gate line and formed from a transparent conductive film included in the gate line, and a data pad connected to the data line and formed from the transparent conductive film, and a color filter array substrate joined with the thin film transistor array substrate to be opposed to each other, wherein the protective film is provided at an area where it overlaps with the color filter array substrate to expose the transparent conductive films included in the gate pad and the data pad.

The present invention claims the benefit of Korean Patent ApplicationNo. P2003-71377, filed in Korea on Oct. 14, 2003, which is herebyincorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a liquid crystal display (LCD) deviceand a method of fabricating an LCD device, and more particularly to anLCD panel device and a fabricating method of fabricating an LCD paneldevice.

2. Description of the Related Art

In general, an LCD device controls transmission of light through liquidcrystal material by application of an electric field thereto, therebydisplaying an image. The LCD device drives the liquid crystal materialby varying the electric field formed between a pixel electrode and acommon electrode arranged in opposition to each other on upper and lowersubstrates.

The LCD device includes a lower array substrate (i.e., thin filmtransistor (TFT) array substrate) and an upper array substrate (i.e.,color filter array substrate) that are coupled together. Accordingly, aspacer is disposed between the upper and lower substrates in order tomaintain a uniform cell gap between the upper and lower substrates,wherein a liquid crystal material is filled within the cell gap.

The lower array substrate includes a plurality of signal wirings andTFTs, and an alignment film coated thereon to maintain alignment of theliquid crystal material. The upper array substrate includes a colorfilter for producing colored light, a black matrix for preventing lightleakage, and an alignment film coated thereon to maintain alignment ofthe liquid crystal material.

Fabrication of the lower array substrate includes relatively complicatedfabrication processes, such as various semiconductor processes thatrequire a plurality of mask processes, thereby increasing manufacturingcost of the LCD panel device. Consequently, development of the lowerarray substrate has been directed toward reducing the total number ofindividual mask processes. For example, a single mask process mayinclude many various sub-processes, such as thin film deposition,cleaning, photolithography, etching, photo-resist stripping, andinspection. Presently, a four-round mask process has been developed thatexcludes one mask process from the currently-used five-round maskprocess.

FIG. 1 is a plan view of a lower array substrate of an LCD panel deviceaccording to the related art, and FIG. 2 is a cross sectional view alongII-II′ of FIG. 1 according to the related art. In FIGS. 1 and 2, a lowerarray substrate of an LCD panel device includes a gate line 2 and a dataline 4 provided on a lower substrate 1 in such a manner as to intersecteach other having a gate insulating film 12 therebetween, a TFT 30provided at each of the intersections, a pixel electrode 22 provided ata cell area defined by the intersections, a storage capacitor 40provided at an overlapping portion between the gate line 2 and a storageelectrode 28, a gate pad 50 connected to the gate line 2, and a data pad60 connected to the data line 4. Accordingly, the gate line 2 transmitsgate signals and the data line 4 transmits data signals.

The TFT 30 allows a pixel signal transmitted along the data line 4 to becharged into the pixel electrode 22 and maintained in response to a gatesignal transmitted along the gate line 2. The TFT 30 includes a gateelectrode 6 connected to the gate line 2, a source electrode 8 connectedto the data line 4, and a drain electrode 10 connected to the pixelelectrode 22. Furthermore, the TFT 30 includes an active layer 14overlapping the gate electrode 6 and having a gate insulating film 12therebetween to define a channel between the source electrode 8 and thedrain electrode 10. In addition, the active layer 14 overlaps with thedata line 4, a lower data pad electrode 62, and a storage electrode 28.Furthermore, an ohmic contract layer is provided on the active layer 14for making electrical contact with the data line 4, the source electrode8, the drain electrode 10, the lower data pad electrode 62, and thestorage electrode 22.

The pixel electrode 22 is connected, via a first contact hole 20 passingthrough a protective film 18, to the drain electrode 10 of the thin filmtransistor 30, and is provided at a pixel area 5. Accordingly, anelectric field is created between the pixel electrode 22 to which apixel signal is supplied via the TFT 30 and a common electrode (notshown) to which a reference voltage is supplied. Thus, liquid crystalmolecules between the lower array substrate and the upper arraysubstrate are rotated by such the electric field due to a dielectricanisotropy of the liquid crystal material. Therefore, lighttransmittance through the pixel area 5 is differentiated depending upona degree of rotation of the liquid crystal molecules, therebyimplementing a gray level scale.

The storage capacitor 40 includes the gate line 2, a storage electrode28 overlapping with the gate line 2 having the gate insulating film 12,the active layer 14, and the ohmic contact layer 16 therebetween.Accordingly, the storage electrode 28 is connected, via a second contacthole 42 defined at the protective film 18, to the pixel electrode 22.Thus, the storage capacitor 40 allows a pixel signal charged to thepixel electrode 22 to be maintained until the next subsequent pixelsignal is charged to the pixel electrode 22.

The gate pad 50 is connected to a gate driver (not shown) to supply gatesignals to the gate line 2, and includes a lower gate pad electrode 52extending from the gate line 2, and an upper gate pad electrode 54connected, via a third contact hole 56 passing through the gateinsulating film 12 and the protective film 18, to the lower gate padelectrode 52.

The data pad 60 is connected to a data driver (not shown) to supply datasignals to the data line 4, and includes a lower data pad electrode 62extending from the data line 4, and an upper data pad electrode 64connected, via a fourth contact hole 66 passing through the protectivefilm 18, to an upper data pad electrode 64 connected to the lower datapad electrode 62.

FIGS. 3A to 3D are cross sectional views of a method of fabricating thelower array substrate of FIG. 2 according to the related art. In FIG.3A, gate metal patterns including the gate line 2, the gate electrode 6,and the lower gate pad electrode 52 are provided on the lower substrate1 using a first mask process. For example, a gate metal layer is formedon the lower substrate 1 by a deposition technique, such as sputtering.Then, the gate metal layer is patterned by photolithography and theetching process using a first mask to form gate metal patterns includingthe gate line 2, the gate electrode 6, and the lower gate pad electrode52. The gate metal layer is made from an aluminum group metal.

In FIG. 3B, the gate insulating film 12 is coated onto the lowersubstrate 1 provided with the gate metal patterns. Then, semiconductorpatterns including the active layer 14 and the ohmic contact layer 16,and data patterns including the data line 4, the source electrode 8, thedrain electrode 10, the lower data pad electrode 62, and the storageelectrode 28 are formed on the gate insulating film 12 by a second maskprocess. For example, the gate insulating film 12, an amorphous siliconlayer, an n⁺ amorphous silicon layer, and a data metal layer aresequentially provided on the lower substrate 1 provided with the gatemetal patterns by deposition techniques, such as plasma enhancedchemical vapor deposition (PECVD) and sputtering. Accordingly, the gateinsulating film 12 is formed from an inorganic insulating material, suchas silicon nitride (SiN_(x)) or silicon oxide (SiO_(x)), and the datametal is selected from molybdenum (Mo), titanium (Ti), tantalum (Ta), ora molybdenum alloy.

Then, a photo-resist pattern is formed on the data metal layer byphotolithography using a second mask. For example, a diffractiveexposure mask having a diffractive exposing part at a channel portion ofa TFT is used as a second mask, thereby allowing a photo-resist patternof the channel portion to have a lower height than other source/drainpattern portion. Subsequently, the data metal layer is patterned by awet etching process using the photo-resist pattern to provide the datapatterns including the data line 4, the source electrode 8, the drainelectrode 10, which is integral to the source electrode 8, and thestorage electrode 28.

Next, the n⁺ amorphous silicon layer and the amorphous silicon layer aresimultaneously patterned by a dry etching process using the samephoto-resist pattern to provide the ohmic contact layer 14 and theactive layer 16. The photo-resist pattern having a relatively low heightis removed from the channel portion by an ashing process and the datametal layer and the ohmic contact layer 16 of the channel portion areetched by the dry etching process. Thus, the active layer 14 of thechannel portion is exposed to disconnect the source electrode 8 from thedrain electrode 10. Then, the photo-resist pattern left on the datapattern group is removed by a stripping process.

In FIG. 3C, the protective film 18 including the first, second, third,and fourth contact holes 20, 42, 56, and 66 are formed on the gateinsulating film 12 provided with the data patterns. For example, theprotective film 18 is entirely formed on the gate insulating film 12provided with the data patterns by a deposition technique, such as theplasma enhanced chemical vapor deposition (PECVD). Then, the protectivefilm 18 is patterned by photolithography and etching processes using athird mask to define the first, second, third, and fourth contact holes20, 42, 56, and 66. The first contact hole 20 passes through theprotective film 18 to expose the drain electrode 10, whereas the secondcontact hole 42 passes through the protective film 18 to expose thestorage electrode 28. The third contact hole 56 passes through theprotective film 18 and the gate insulating film 12 to expose the lowergate pad electrode 52, whereas the fourth contact hole 66 passes throughthe protective film 18 to expose the lower data pad electrode 62.Accordingly, when a metal having a large dry etching ratio, such asmolybdenum (Mo), is used as the data metal, the first, second, andfourth contact holes 20, 42, and 66 pass through the drain electrode 10,the storage electrode 28, and the lower data pad electrode 62,respectively, to expose side surfaces thereof. The protective film 18 ismade from an inorganic insulating material identical to the gateinsulating film 12, or an organic insulating material, such as anacrylic organic compound having a small dielectric constant,benzocyclobutene (BCB), or (perfluorocyclobutane (PFCB).

In FIG. 3D, transparent conductive patterns including the pixelelectrode 22, the upper gate pad electrode 54, and the upper data padelectrode 64 are provided on the protective film 18 by a fourth maskprocess. For example, a transparent conductive film is coated onto theprotective film 18 by a deposition technique, such as sputtering. Then,the transparent conductive film is patterned by photolithography andetching processes using a fourth mask to provide the transparentconductive patterns including the pixel electrode 22, the upper gate padelectrode 54, and the upper data pad electrode 64. The pixel electrode22 is electrically connected, via the first contact hole 20, to thedrain electrode 10 while being electrically connected, via the secondcontact hole 42, to the storage electrode 28. The upper gate padelectrode 54 is electrically connected, via the third contact hole 56,to the lower gate pad electrode 52, and the upper data pad electrode 64is electrically connected, via the fourth contact hole 66, to the lowerdata pad electrode 62. The transparent conductive film is formed fromindium-tin-oxide (ITO), tin-oxide (TO), indium-tin-zinc-oxide (ITZO), orindium-zinc-oxide (IZO).

The method of fabricating the lower array substrate according to therelated art adopts the four-round mask process, thereby reducing thenumber of fabricating processes and reducing manufacturing costsproportional to the total number of fabricating processes, as comparedto the five-round mask process. However, since the four-round maskprocess is complicated, cost reduction is limited. Thus, furthersimplification of the fabricating processes are necessary to furtherreduce manufacturing costs.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to an LCD panel deviceand method of fabricating an LCD panel device that substantiallyobviates one or more of the problems due to limitations anddisadvantages of the related art.

An object of the present invention is to provide an LCD panel devicefabricated using a reduced number of mask processes.

Another object of the present invention is to provide a method offabricating an LCD panel device having a reduced number of maskprocesses.

Additional features and advantages of the invention will be set forth inthe description which follows, and in part will be apparent from thedescription, or may be learned by practice of the invention. Theobjectives and other advantages of the invention will be realized andattained by the structure particularly pointed out in the writtendescription and claims hereof as well as the appended drawings.

To achieve these and other advantages and in accordance with the purposeof the present invention, as embodied and broadly described, a liquidcrystal display panel device includes a thin film transistor arraysubstrate having a gate line provided on a substrate, a data lineintersecting the gate line and having a gate insulating pattern disposedtherebetween to define a pixel area, a thin film transistor provided atthe intersection between the gate line and the data line, a protectivefilm for protecting the thin film transistor, a pixel electrode providedat the pixel area and connected to the thin film transistor, a gate padconnected to the gate line and formed from a transparent conductive filmincluded in the gate line, and a data pad connected to the data line andformed from the transparent conductive film, and a color filter arraysubstrate joined with the thin film transistor array substrate to beopposed to each other, wherein the protective film is provided at anarea where it overlaps with the color filter array substrate to exposethe transparent conductive films included in the gate pad and the datapad.

In another aspect, a liquid crystal display panel device includes a gateline provided on a substrate, a data line intersecting the gate lineinsulated from the gate line to define a pixel area, a thin filmtransistor provided at the intersection between the gate line and thedata line, a pixel electrode connected to the thin film transistor andprovided at the pixel area, a gate pad connected to the gate line andformed from a transparent conductive film included in the gate line, adata pad connected to the data line and formed from the transparentconductive film, an alignment film provided at an area other than a padarea including the gate pad and the data pad, and a protective filmprovided at a lower portion of the alignment film in the same pattern asthe alignment film to expose the transparent conductive films of thegate pad and the data pad.

In another aspect, a method of fabricating a liquid crystal displaypanel device includes providing a lower array substrate having a gateline provided on a substrate, a data line intersecting the gate line andhaving a gate insulating pattern disposed therebetween to define a pixelarea, a thin film transistor provided at the intersection between thegate line and the data line, a protective film for protecting the thinfilm transistor, a pixel electrode provided at the pixel area andconnected to the thin film transistor, a gate pad connected to the gateline and formed from a transparent conductive film included in the gateline, and a data pad connected to the data line and formed from thetransparent conductive film, providing a color filter array substrateopposed to the thin film transistor array substrate, joining the thinfilm transistor array substrate with the color filter array substrate toexpose a pad area including the gate pad and the data pad, and exposingthe transparent conductive film at the pad area using the color filterarray substrate as a mask.

In another aspect, a method of fabricating a liquid crystal displaypanel device includes providing a lower array substrate having a gateline provided on a substrate, a data line intersecting the gate line andhaving a gate insulating pattern disposed therebetween to define a pixelarea, a thin film transistor provided at the intersection between thegate line and the data line, a protective film for protecting the thinfilm transistor, a pixel electrode provided at the pixel area andconnected to the thin film transistor, a gate pad connected to the gateline and formed from a transparent conductive film included in the gateline, and a data pad connected to the data line and formed from thetransparent conductive film, providing a color filter array substrateopposed to the thin film transistor array substrate, joining the thinfilm transistor array substrate with the color filter array substrate toexpose a pad area including the gate pad and the data pad, and exposingthe transparent conductive film at the pad area using the color filterarray substrate as a mask.

In another aspect, a method of fabricating a liquid crystal displaypanel device includes forming gate patterns having a gate line, a gateelectrode, a gate pad, and a data pad including a transparent conductivefilm and a pixel electrode on a substrate, forming a semiconductorpattern and a gate insulating pattern on the substrate provided with thegate patterns and the pixel electrode and exposing transparentconductive films included in the data pad, the gate pad, and the pixelelectrode, forming a data pattern including the data line, a sourceelectrode, and a drain electrode on the substrate provided with thesemiconductor pattern and the gate insulating pattern, forming aprotective film along an entire surface of the substrate to protect thethin film transistor, forming an alignment film on the protective filmat a remaining area other than a pad area including the gate pad and thedata pad, and removing the protective film to cover the pad area usingthe alignment film as a mask to expose the transparent conductive filmincluded in the pad area.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a furtherunderstanding of the invention and are incorporated in and constitute apart of this specification, illustrate embodiments of the invention andtogether with the description serve to explain the principles of theinvention. In the drawings:

FIG. 1 is a plan view of a lower array substrate of an LCD panel deviceaccording to the related art;

FIG. 2 is a cross sectional view along II-II′ of FIG. 1 according to therelated art;

FIGS. 3A to 3D are cross sectional views of a method of fabricating thelower array substrate of FIG. 2 according to the related art;

FIG. 4 is a plan view of an exemplary lower array substrate of an LCDpanel device according to the present invention;

FIG. 5 is a cross sectional view of the lower array substrate along V-V′of FIG. 4 according to the present invention;

FIGS. 6A and 6B are plan and cross sectional views of an exemplaryredundancy line according to the present invention;

FIGS. 7A and 7B are plan and cross sectional views of an exemplary firstmask process of an exemplary method of fabricating a lower arraysubstrate according to the present invention;

FIGS. 8A and 8B are plan and cross sectional views of an exemplarysecond mask process of an exemplary method of fabricating a lower arraysubstrate according to the present invention;

FIGS. 9A to 9C are cross sectional views of the exemplary second maskprocess of FIGS. 8A and 8B according to the present invention;

FIGS. 10A and 10B are plan and cross sectional views of an exemplarythird mask process of an exemplary method of fabricating a lower arraysubstrate according to the present invention;

FIGS. 11A to 11E are cross sectional views of the exemplary third maskprocess of FIGS. 9A and 9B according to the present invention;

FIG. 12 is a cross sectional view of an exemplary LCD panel deviceincluding the exemplary lower array substrate of FIG. 5 according to thepresent invention;

FIG. 13 is a cross sectional view of another exemplary LCD panel deviceincluding the lower array substrate of FIG. 5 according to the presentinvention;

FIG. 14 is a plan view of another exemplary lower array substrate of anLCD panel device according to the present invention;

FIG. 15 is a cross sectional view along of the lower array substratetaken along XV1-XV1′ and XV2-XV2′ of FIG. 14 according to the presentinvention;

FIGS. 16A to 16C are cross sectional views of an exemplary method offabricating the lower array substrate of FIG. 15 according to thepresent invention;

FIGS. 17A to 17E are cross sectional views of an exemplary third maskprocess of FIG. 16C according to the present invention;

FIG. 18 is a cross sectional view of an exemplary LCD panel deviceincluding the exemplary lower array substrate of FIG. 15 according tothe present invention; and

FIG. 19 is a cross sectional view of another exemplary LCD panel deviceincluding the exemplary lower array substrate of FIG. 15 according tothe present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Reference will now be made in detail to the preferred embodiments of thepresent invention, examples of which are illustrated in the accompanyingdrawings.

FIG. 4 is a plan view of an exemplary lower array substrate of an LCDpanel device according to the present invention, and FIG. 5 is a crosssectional view of the lower array substrate along V-V′ of FIG. 4according to the present invention. In FIGS. 4 and 5, a lower arraysubstrate may include a gate line 102 and a data line 104 provided on alower substrate 101 in such a manner to intersect each other with havinga gate insulating pattern 112 therebetween, a TFT 130 provided at eachof the intersections, a pixel electrode 122 provided at a pixel area 105defined by the intersections, a storage capacitor 140 provided at anoverlapping portion between the pixel electrode 122 and the gate line102, a gate pad 150 extending from the gate line 102, and a data pad 160extending from the data line 104. The gate line 102 may transmit gatesignals and the data line 104 may transmit data signals.

The TFT 130 passes pixel signals transmitted along the data line 104 tobe charged into the pixel electrode 122, and are maintained in responseto gate signals transmitted along the gate line 102. Accordingly, theTFT 130 may include a gate electrode 106 connected to the gate line 102,a source electrode 108 connected to the data line 104, and a drainelectrode 110 connected to the pixel electrode 122. Furthermore, the TFT130 may include semiconductor patterns 114 and 116 overlapping with thegate electrode 106 and having the gate insulating pattern 112therebetween to define a channel between the source electrode 108 andthe drain electrode 110.

The gate pattern may include the gate electrode 106 and the gate line102 and may include a structure in which a transparent conductive film170 and a gate metal film 172 may be disposed thereupon. Thesemiconductor pattern may form a channel between the source electrode108 and the drain electrode 110, and may include an active layer 114partially overlapping with the gate pattern and having the gateinsulating film 112 therebetween. Furthermore, the semiconductor patternmay be formed on the active layer 114, and may include an ohmic contactlayer 116 for making ohmic contact with the data line 104, the storageelectrode 128, the source electrode 108, and the drain electrode 110.The semiconductor pattern may be formed separately between adjacentcells to prevent signal interference between the adjacent cells causedby the semiconductor pattern.

The pixel electrode 122 may be formed from the transparent conductivefilm 170 at the pixel area 105 to be directly connected to the drainelectrode 110 of the thin film transistor 130. Accordingly, an electricfield may be formed between the pixel electrode 122 to which pixelsignals may be supplied via the TFT 130 and a common electrode (notshown) supplied with a reference voltage. Thus, the electric field mayrotate liquid crystal molecules of a liquid crystal material disposedbetween the upper array substrate and the lower array substrate due todielectric anisotropy of the liquid crystal material. Lighttransmittance through the pixel area 105 may be differentiated dependingupon a rotation degree of the liquid crystal molecules, therebyimplementing a gray level scale.

The storage capacitor 140 may include the gate line 102, and a storageelectrode 128 overlapping with the gate line 102 and having the gateinsulating film 112, the active layer 114, and the ohmic contact layer116 therebetween, and may be directly connected to the pixel electrode122. Accordingly, the storage capacitor 140 may allow a pixel signalcharged in the pixel electrode 122 to be stably maintained until thenext subsequent pixel signal is charged in the pixel electrode 122.

The gate pad 150 may be connected to a gate driver (not shown) to supplygate signals generated from the gate driver, via a gate link 152, to thegate line 120. The gate pad 150 may have a structure in which thetransparent conductive film 170 extending from the gate link 152connected to the gate line 102 may be exposed. Accordingly, the gatelink 152 may include the transparent conductive film 170 and the gatemetal layer 172 formed on the transparent conductive film 170.

The data pad 160 may be connected to a data driver (not shown) to supplydata signals generated from the data driver, via a data link 168, to thedata line 104. The data pad 160 may have a structure in which thetransparent conductive film 170 extending from the data link 168connected to the data line 104 may be exposed. Accordingly, the datalink 168 may include a lower data link electrode 162 formed from thetransparent conductive film 170 and an upper data link electrode 166connected to the data line 104.

FIGS. 6A and 6B are plan and cross sectional views of an exemplaryredundancy line according to the present invention. In FIGS. 6A and 6B,a lower array substrate 101 may include a redundancy line 290 that maybe directly connected to the data line 104, and may have a width lessthan a width of the data line 104 in order to compensate for aresistance of the data line 104. For example, the redundancy line 290may be formed from the transparent conductive film 170.

FIGS. 7A and 7B are plan and cross sectional views of an exemplary firstmask process of an exemplary method of fabricating a lower arraysubstrate according to the present invention. In FIGS. 7A and 7B, alower substrate 101 may include a pixel electrode 122, a gate patternincluding a gate line 102, a gate electrode 106, a gate link 152, a gatepad 150, a data pad 160, a lower data link electrode 162, and aredundancy line (not shown), each of which may have a double-layerstructure, and may be formed using a first mask process. For example, atransparent conductive film 170 and a gate metal film 172 may besequentially formed on the lower substrate 101 by a depositiontechnique, such as sputtering. The transparent conductive film 170 maybe made from a transparent conductive material, such as indium-tin-oxide(ITO), tin-oxide (TO), indium-tin-zinc-oxide (ITZO), indium-zinc-oxide(IZO), and the gate metal film 172 may include a metal, such as analuminum group metal including aluminum/neodymium (AlNd), molybdenum(Mo), copper (Cu), chromium (Cr), tantalum (Ta), and titanium (Ti).

Then, the transparent conductive film 170 and the gate metal layer 172may be patterned by photolithography and etching processes using a firstmask to provide the gate line 102, the gate electrode 106, the gate link152, and the lower data link electrode 162, each of which may have adouble-layer structure; and the gate pad 150 including the gate metalfilm 172, the data pad 160, and the pixel electrode 122.

FIGS. 8A and 8B are plan and cross sectional views of an exemplarysecond mask process of an exemplary method of fabricating a lower arraysubstrate according to the present invention. In FIGS. 8A and 8B, a gateinsulating pattern 112, and a semiconductor pattern including an activelayer 114 and an ohmic contact layer 116 may be formed on a lowersubstrate 101 provided with a gate pattern using a second mask process.The gate metal films 172 included in the data pad 160, the lower datalink electrode 162, the gate pad 150, and the pixel electrode may beremoved to expose the transparent conductive film 170.

FIGS. 9A to 9C are cross sectional views of the exemplary second maskprocess of FIGS. 8A and 8B according to the present invention. In FIG.9A, a gate insulating film 111 and first and second semiconductor layers115 and 117 may be sequentially formed on a lower substrate 101 providedwith the gate pattern using a deposition technique, such as PEVCD orsputtering. For example, the gate insulating film 111 may be made froman inorganic insulating material, such as silicon nitride (SiN_(x)) orsilicon oxide (SiO_(x)). In addition, the first semiconductor layer 115may be formed from undoped amorphous silicon and the secondsemiconductor layer 117 may be formed from amorphous silicon doped withan N-type or P-type impurities. Subsequently, a photo-resist film 316may be formed along an entire surface of the second semiconductor layer117, and a second mask 300 may be aligned at the upper portion of thelower substrate 101. The second mask 300 may include a mask substrate302 made from a transparent material, and a shielding part 314 providedat a shielding area S2 of the mask substrate 302. Accordingly, anexposure area of the mask substrate 302 may become an exposure area S1.

In FIG. 9B, the photo-resist film 316 using the second mask 300 may beexposed to light and developed, thereby providing a photo-resist pattern318 corresponding to the shielding part 314 of the second mask 300.Then, the gate insulating film 111 and the first and secondsemiconductor layers 115 and 117 may be patterned by an etching processusing the photo-resist pattern 318. As a result, the gate insulatingpattern 112 may overlap the gate pattern including the gate line 102,the gate electrode 106, and the gate link 152, and the semiconductorpattern may include the active layer 114 and the ohmic contact layer 116and may have a width greater than a width of the gate pattern on thegate pattern, as shown in FIG. 9C. Thus, deterioration of channelcharacteristics occurring when the semiconductor pattern has a widthless than a width of the gate electrode 106 may be prevented.

Then, the exposed gate metal film 172 may be removed by wet etchingusing the gate insulating pattern 112 and the semiconductor pattern 114and 116 as a mask. For example, the gate metal films 172 included in thegate pad 150, the data pad 160, the lower data link electrode 162, andthe pixel electrode 122 may be removed to expose the transparentconductive films 170 included therein.

FIGS. 10A and 10B are plan and cross sectional views of an exemplarythird mask process of an exemplary method of fabricating a lower arraysubstrate according to the present invention. In FIGS. 10A and 10B, adata pattern including the data line 104, the source electrode 108, thedrain electrode 110, the storage electrode 128, and the upper data linkelectrode 166 may be formed on the lower substrate 101 provided with thegate insulating pattern 112 and the semiconductor pattern using a thirdmask process.

FIGS. 11A to 11E are cross sectional views of the exemplary third maskprocess of FIGS. 9A and 9B according to the present invention. In FIG.11A, a data metal layer 109 and a photo-resist film 328 may besequentially formed on the lower substrate 101 provided with thesemiconductor pattern by a deposition technique, such as sputtering. Forexample, the data metal layer 109 may be formed from a metal, such asmolybdenum (Mo), copper (Cu) or the like.

Then, a third mask 320 that is a partial exposure mask may be aligned atthe upper portion of the lower substrate 101. The third mask 320 mayinclude a mask substrate 322 made from a transparent material, ashielding part 324 provided at a shielding area S2 of the mask substrate322, and a diffractive exposure part (or transflective part) 326provided at a partial exposure area S3 of the mask substrate 322.Accordingly, the exposed area of the mask substrate 322 may become theexposure area S1.

In FIG. 11B, the photo-resist film 328 using the third mask 320 may beexposed to light and developed, thereby providing a photo-resist pattern330 having step coverage at the shielding area S2 and the partialexposure area S3 corresponding to the shielding part 324 and thediffractive exposure part 326 of the third mask 320. For example, thephoto-resist pattern 330 provided at the partial exposure area S3 mayhave a second height lower than a first height of the photo-resistpattern 330 provided at the shielding area S2.

The data metal layer 109 (in FIG. 11A) may be patterned by a wet etchingprocess using the photo-resist pattern 330 as a mask to provide a datapattern including the storage electrode 128, the data line 104, thesource electrode 108, and the drain electrode 110 connected to one sideof the data line 104 and the upper data link electrode 166 connected toother side of the data line 104.

Next, the active layer 114 and the ohmic contact layer 116 may be formedalong the data pattern by dry etching using the photo-resist pattern 330as a mask. Accordingly, portions of the active layer 114 and the ohmiccontact layer 116 positioned at the remaining area other than the activelayer 114 and the ohmic contact layer 116 overlapping with the datapattern may be removed. Thus, a short between adjacent cells may beprevented due to the semiconductor pattern including the active layer114 and the ohmic contact layer 116.

In FIG. 11C, the photo-resist pattern 230 having the second height atthe partial exposure area S3 may be formed by an ashing process using anoxygen (O₂) plasma, whereas a height of the photo-resist pattern 330 (inFIG. 11B) having the first height at the shielding area S2 may bereduced. The data metal layer and the ohmic contact layer 116 providedat the partial exposure area S3, i.e., at the channel portion of theTFT, may be removed by an etching process using the photo-resist pattern330, thereby disconnecting the drain electrode 110 from the sourceelectrode 108.

In FIG. 11D, the photo-resist pattern 230 left on the data pattern maybe removed by a stripping process.

In FIG. 11E, a protective film 118 may be formed along an entire surfaceof the substrate 101 provided with the data pattern. The protective film118 may be made from an inorganic insulating material identical to thegate insulating pattern 112, or an organic insulating material, such asan acrylic organic compound having a small dielectric constant,benzocyclobutene (BCB) or perfluorocyclobutane (PFCB).

FIG. 12 is a cross sectional view of an exemplary LCD panel deviceincluding the exemplary lower array substrate of FIG. 5 according to thepresent invention. In FIG. 12, an LCD panel device may include an upperarray substrate 300 and a lower array substrate 302 that are joined toeach other by a sealant 354. The upper array substrate 300 may includean upper array 352 including black matrices, color filters, and commonelectrodes provided on an upper substrate 350. The lower array substrate302 may be provided such that an area thereof overlapping with the upperarray substrate 300 may be protected by a protective pattern 304 and thetransparent conductive film 170 included in at least one of the gate pad150, the data pad 160, and the common pad 180 at a pad area that doesnot overlap with the upper array substrate 300 may be exposed.

An exemplary method of fabricating an LCD panel device may includeseparate preparation of the upper array substrate 300 and the lowerarray substrate 302, joining together of the upper and lower arraysubstrates 300 and 302 using a sealant 354. Then, a protective film 118of the lower array substrate 302 may be patterned by a pad openingprocess using the lower array substrate 300 as a mask to provide aprotective pattern 304 at the display area and expose the transparentconductive film 170 included in any one of the gate pad 150, the datapad 160, and the common pad 180 at the pad area.

Next, the pad opening process may sequentially scan each pad exposed bythe upper array substrate 300 using a plasma generated by an atmosphereplasma generator, or may collectively scan each pad, thereby exposingthe transparent conductive films 170 of the gate pad 150 and the datapad 160. Alternatively, a plurality of liquid crystal cells made by ajoining of the upper array substrate 300 with the lower array substrate302 may be introduced into a chamber. Then, the protective film 118 atthe pad area may be exposed by the upper array substrate 300 using anormal-pressure plasma, thereby exposing the transparent conductivefilms 170 of the gate pad 150 and the data pad 160. Furthermore, theentire LCD panel device in which the upper array substrate 300 and thelower array substrate 302 are joined with each other may be immersedinto an etching liquid. Alternatively, the pad area including the gatepad 150, the data pad 160, and the common pad 180 may only be immersedinto the etching liquid, thereby exposing the transparent conductivefilms 170 of the gate pad 150 and the data pad 160.

FIG. 13 is a cross sectional view of another exemplary LCD panel deviceincluding the lower array substrate of FIG. 5 according to the presentinvention. In FIG. 13, an LCD panel device may include a upper arraysubstrate 300 and a lower array substrate 302 that are joined to eachother by a sealant 354. The lower array substrate 302 may be providedsuch that a display area defined by an alignment film 382 may beprotected by a protective pattern 304. In addition, the transparentconductive film 170 included in any one of the gate pad 150, the datapad 160, and the common pad at a pad area included in an area where itdoes not overlap with the alignment film 382 may be exposed. In theupper array substrate 300, an upper array 352 may include blackmatrices, color filters, and common electrodes provided on an uppersubstrate 350.

An exemplary method of fabricating an LCD panel device may include alower array substrate 302 formed by first, second, and third maskprocesses. The lower array substrate 302 may be cleaned by a cleaningliquid, and an alignment film 382, such as polyimide, may be printed onthe remaining area other than the pad area. The protective film 118 atthe pad area may be patterned by an etching process using the alignmentfilm 282 as a mask to provide the protective pattern 304 for exposingthe transparent conductive films 170 of the gate pad 150 and the datapad 160. A gas used upon the etching process may include SF₆. Next, thealignment film 382 may be rubbed along a predetermined direction, andthe lower array substrate 302 with the alignment film 382 may be joinedwith a separately prepared upper array substrate 300 to complete the LCDpanel device.

FIG. 14 is a plan view of another exemplary lower array substrate of anLCD panel device according to the present invention, and FIG. 15 is across sectional view along of the lower array substrate taken alongXV1-XV1′ and XV2-XV2′ of FIG. 14 according to the present invention. InFIGS. 14 and 15, a lower array substrate may include a gate line 202 anda data line 204 provided on a lower substrate 101 in such a manner tointersect each other and having a gate insulating pattern 212therebetween, a TFT 230 provided at each of the intersections, a pixelelectrode 222 and a common electrode 284 provided at a pixel area 205defined by the intersections in such a manner to make a horizontalelectric field, and a common line 286 connected to the common electrode284. Furthermore, the lower array substrate may include a storagecapacitor 240 provided at an overlapping portion between a storageelectrode 228 and the common line 286, a gate pad 250 extending from thegate line 202, a data pad 260 extending from the data line 204, and acommon pad 280 extending from the common line 286. The gate line 202 maysupply gate signals and the data line 204 may supply data signals. Inaddition, the common line 286 may supply a reference voltage for drivingliquid crystal material, and may be provided in parallel to the gateline 202 with the pixel area 205 disposed therebetween.

The TFT 230 may allow pixel signals transmitted along the data line 204to be charged to the pixel electrode 222, and may be maintained inresponse to gate signals transmitted along the gate line 202.Accordingly, the TFT 230 may include a gate electrode 206 connected tothe gate line 202, a source electrode 208 connected to the data line204, and a drain electrode 210 connected to the pixel electrode 222.Furthermore, the TFT 230 may include an active layer 214 overlappingwith the gate electrode 206 and having the gate insulating pattern 212therebetween to define a channel between the source electrode 208 andthe drain electrode 210, wherein the active layer 214 may also overlapthe storage electrode 228. In addition, an ohmic contact layer 216 formaking electrical contact to the drain electrode 210 and the storageelectrode 228 may be provided on the active layer 214.

The pixel electrode 222 may be integral to both the drain electrode 210of the TFT 230 and the storage electrode 228 to be provided at the pixelarea 205. For example, the pixel electrode 222 may include a horizontalpart 222 a that may extend from the drain electrode 210 in parallel toan adjacent gate line 202, and a finger part 222 b that may extend alonga vertical direction from the horizontal part 222 a. In addition, thecommon electrode 284 may be connected to the common line 286 to beprovided at the pixel area 205. For example, the common electrode 284may be provided in parallel to the finger part 222 b of the pixelelectrode 222 at the pixel area 205. Accordingly, an electric field maybe generated between the pixel electrode 222 to which pixel signals maybe applied via the TFT 230 and the common electrode 284 to which areference voltage may be supplied via the common line 286. For example,a horizontal electric field may be formed between the finger part 222 bof the pixel electrode 222 and the common electrode 284. Accordingly,the electric field may rotate liquid crystal molecules of a liquidcrystal material between the upper array substrate and the lower arraysubstrate due to dielectric anisotropy of the liquid crystal material.Thus, light transmittance through the pixel area 205 may bedifferentiated depending upon a degree of rotation of the liquid crystalmolecules, thereby implementing a gray level scale.

The storage capacitor 240 may include the gate line 202, and the storageelectrode 228 overlapping with the gate line 202 and having the gateinsulating film 212, the active layer 214, and the ohmic contact layer216 disposed therebetween, and may be integral to the pixel electrode222. The storage capacitor 240 may allow a pixel signal charged in thepixel electrode 222 to be stably maintained until the next subsequentpixel signal is charged in the pixel electrode 222.

The gate pad 250 may be connected to a gate driver (not shown) to supplygate signals generated from the gate driver, via a gate link 252, to thegate line 202. The gate pad 250 may have a structure in which thetransparent conductive film 170 extending from the gate link 252connected to the gate line 202 may be exposed. Accordingly, the gatelink 252 may include the transparent conductive film 170, and the gatemetal layer 172 formed on the transparent conductive film 170.

The data pad 260 may be connected to a data driver (not shown) to supplydata signals generated from the data driver, via a data link 268, to thedata line 204. The data pad 260 may have a structure in which thetransparent conductive film 170 extending from the data link 268connected to the data line 204 may be exposed. Accordingly, the datalink 268 may include a lower data link electrode 262 having thetransparent conductive film 170 and the data metal layer 172 formed onthe transparent conductive film 170, and an upper data link electrode266 connected to the data line 204.

The common pad 280 may be connected to the gate driver (not shown) tosupply gate signals generated from the gate driver, via a common link282, to the common line 286. The common pad 280 may have a structure inwhich the transparent conductive film 170 extending from the common link282 connected to the common line 286 may be exposed. Accordingly, thecommon link 282 may include the transparent conductive film 170, and thegate metal layer 172 formed on the transparent conductive film 170.

FIGS. 16A to 16C are cross sectional views of an exemplary method offabricating the lower array substrate of FIG. 15 according to thepresent invention. In FIG. 16A, the pixel electrode 222 (in FIG. 14),the gate pattern including the gate line 202, the gate electrode 206,the gate link 252, the gate pad 250, the data pad 260, the lower datalink electrode 262, the common electrode 284, the common line 286 (inFIG. 14), the common link 282, and the common pad 280, each of which mayhave a double-layer structure, may be formed on the lower substrate 101using a first mask process. For example, the transparent conductive film170 and the gate metal film 172 may be sequentially formed on the lowersubstrate 101 by a deposition technique, such as sputtering.Accordingly, the transparent conductive film 170 may be made from atransparent conductive material, such as indium-tin-oxide (ITO),tin-oxide (TO), indium-tin-zinc-oxide (ITZO), indium-zinc-oxide (IZO) orthe like, while the gate metal film 172 may be made from a metal, suchas an aluminum group metal including aluminum/neodymium (AlNd),molybdenum (Mo), copper (Cu), chromium (Cr), tantalum (Ta), titanium(Ti) or the like.

Then, the transparent conductive film 170 and the gate metal layer 172may be patterned by photolithography and etching processes using a firstmask, thereby providing a gate pattern including the gate line 202, thegate electrode 206, the gate link 252, the gate pad 250, the data pad260, the lower data link electrode 262, the common electrode 284, thecommon line 286 (in FIG. 14), the common link 282, and the common pad280, each of which may have a double-layer structure; and the pixelelectrode 222 including the gate metal film 172.

In FIG. 16B, a gate insulating pattern 212 and a semiconductor patternincluding the active layer 214 and the ohmic contact layer 216 may beformed on the lower substrate 101 provided with the gate pattern by asecond mask process. For example, a gate insulating film and first andsecond semiconductor layers may be sequentially formed on the lowersubstrate 101 provided with the gate pattern by a deposition technique,such as PEVCD or sputtering. Accordingly, the gate insulating film maybe formed from an inorganic insulating material, such as silicon nitride(SiN_(x)) or silicon oxide (SiO_(x)). The first semiconductor layer maybe formed from undoped amorphous silicon and the second semiconductorlayer may be formed from amorphous silicon doped with an N-type orP-type impurities.

Subsequently, the gate insulating film and the first and secondsemiconductor layers may be patterned by an etching process using asecond mask to provide the gate insulating pattern 212 overlapping withthe gate pattern including the gate line 202, the gate electrode 206,the gate link 252, and the common link 282, and the semiconductorpattern including the active layer 214 and the ohmic contact layer 216and having a width greater than a width of the gate pattern on the gateinsulating pattern 212. Accordingly, deterioration of channelcharacteristics occurring when the semiconductor pattern has a widthless than a width of the gate electrode 206 may be prevented.

In FIG. 16C, a data pattern including the data line 204, the sourceelectrode 208, the drain electrode 210, the storage electrode 228, theupper data link electrode 266, and the pixel electrode 222 may be formedon the lower substrate 101 provided with the gate insulating pattern 212and the semiconductor pattern using a third mask process. The gate metalfilms 172 included in the data pad 260, the gate pad 250, the common pad280, and the common electrode 282 may be removed to expose thetransparent conductive film 170.

FIGS. 17A to 17E are cross sectional views of an exemplary third maskprocess of FIG. 16C according to the present invention. In FIG. 17A, adata metal layer 209 and a photo-resist film 378 may be sequentiallyformed on the lower substrate 101 provided with the semiconductorpattern by a deposition technique, such as sputtering. Accordingly, thedata metal layer 209 may be formed from a metal, such as molybdenum(Mo), copper (Cu) or the like. Then, a third mask 370 that is a partialexposure mask may be aligned at the upper portion of the lower substrate101. The third mask 370 may include a mask substrate 372 made from atransparent material, a shielding part 374 provided at a shielding areaS2 of the mask substrate 372, and a diffractive exposure part (ortransflective part) 376 provided at a partial exposure area S3 of themask substrate 372. Accordingly, the exposed area of the mask substrate372 may become the exposure area S1.

In FIG. 17B, the photo-resist film 378 using the third mask 370 may beexposed and developed, thereby providing a photo-resist pattern 360having step coverage at the shielding area S2 and the partial exposurearea S3 corresponding to the shielding part 374 and the diffractiveexposure part 376 of the third mask 370. For example, the photo-resistpattern 360 provided at the partial exposure area S3 may have a secondheight lower than a first height of the photo-resist pattern 360provided at the shielding area S2.

Then, the data metal layer 209 may be patterned by a wet etching processusing the photo-resist pattern 360 as a mask to provide a data patternincluding the storage electrode 228, the data line 204, the sourceelectrode 208, and the drain electrode 210 connected to one side of thedata line 204 and the upper data link electrode 266 connected to otherside of the data line 204. The gate metal film 172 provided at the lowerportion of the data pattern may be removed by utilizing the gateinsulating pattern 212 as a mask to expose the transparent conductivefilms 170 included in the data pad 260, the gate pad 250, the common pad280, and the common electrode 284.

Next, the active layer 214 and the ohmic contact layer 216 my be formedalong the data pattern by dry etching using the photo-resist pattern 360as a mask. Accordingly, the active layer 214 and the ohmic contact layer216 positioned at the remaining area other than the active layer 214 andthe ohmic contact layer 216 overlapping with the data pattern may beremoved. Thus, a short between adjacent cells caused by thesemiconductor pattern including the active layer 214 and the ohmiccontact layer 216 may be prevented.

In FIG. 17C, the photo-resist pattern 360 having the second height h2 atthe partial exposure area S3 may be removed by an ashing process usingan oxygen (O₂) plasma, whereas a height of the photo-resist pattern 360having the first height h1 at the shielding area S2 may be reduced. Thedata metal layer and the ohmic contact layer 216 provided at the partialexposure area S3, that is, at the channel portion of the thin filmtransistor may be removed by an etching process using the photo-resistpattern 360, thereby disconnecting the drain electrode 210 from thesource electrode 208.

In FIG. 17D, the photo-resist pattern 360 remaining on the data patternmay be removed by a stripping process.

In FIG. 17E, a protective film 218 may be formed along an entire surfaceof the substrate 101 provided with the data pattern. The protective film218 may be made from an inorganic insulating material identical to thegate insulating pattern 212, or an organic insulating material, such asan acrylic organic compound having a small dielectric constant,benzocyclobutene (BCB) or perfluorocyclobutane (PFCB).

FIG. 18 is a cross sectional view of an exemplary LCD panel deviceincluding the exemplary lower array substrate of FIG. 15 according tothe present invention. In FIG. 18, an LCD panel includes device mayinclude an upper array substrate 300 and a lower array substrate 302that are joined to each other by a sealant 354. In the upper arraysubstrate 300, an upper array 352 including black matrices, colorfilters, and common electrodes may be provided on an upper substrate350. The lower array substrate 302 may be provided such that an areathereof overlapping with the upper array substrate 300 may be protectedby a protective pattern 304 and the transparent conductive film 170included in any one of the gate pad 250, the data pad 260, and thecommon pad at a pad area that does not overlap with the upper arraysubstrate 300 may be exposed.

An exemplary method of fabricating an LCD panel device may includeseparate preparation of an upper array substrate 300 and a lower arraysubstrate 302, and then the upper and lower array substrates 300 and 302may be joined to each other by the sealant 354. Then, a protective film218 of the lower array substrate 302 may be patterned by a pad openingprocess using the lower array substrate 300 as a mask to provide aprotective pattern 304 at a display area and expose the transparentconductive film 170 included in any at least one of the gate pad 250,the data pad 260, and the common pad at the pad area.

Meanwhile, a pad opening process may sequentially scan each pad exposedby the upper array substrate 300 using a plasma generated by anatmosphere plasma generator, or may collectively scan each pad, therebyexposing the transparent conductive films 170 of the gate pad 250 andthe data pad 260. Alternatively, a plurality of liquid crystal cellsmade by a joining of the upper array substrate 300 with the lower arraysubstrate 302 may be introduced into a chamber. Then, the protectivefilm 218 at the pad area may be exposed by the upper array substrate 300with the aid of a normal-pressure plasma, thereby exposing thetransparent conductive films 170 of the gate pad 250 and the data pad260. Otherwise, the LCD panel device in which the upper array substrate300 and the lower array substrate 302 are joined with each other may beimmersed into an etching liquid, or the pad area including the gate pad250 and the data pad 260 may only be immersed into the etching liquid,thereby exposing the transparent conductive films 170 of the gate pad250 and the data pad 260.

FIG. 19 is a cross sectional view of another exemplary LCD panel deviceincluding the exemplary lower array substrate of FIG. 15 according tothe present invention. In FIG. 19, an LCD panel device may include anupper array substrate 300 and a lower array substrate 302 that arejoined to each other by a sealant 354. The lower array substrate 302 maybe provided such that a display area defined by an alignment film 382may be protected by a protective pattern 304 and the transparentconductive film 170 included in any at least one of the gate pad 250,the data pad 260, and the common pad at a pad area included in an areawhere it does not overlap with the alignment film 382 may be exposed.Accordingly, the protective pattern 304 may be formed by a pattern madeby an etching process using the alignment film 382 as a mask. In theupper array substrate 300, an upper array 352 including black matrices,color filters, and common electrodes may be provided on an uppersubstrate 350.

According to the present invention, a pixel electrode and gate patternmay be formed by a first mask process, a semiconductor pattern may beformed by a second process; and a data pattern may be formed by a thirdmask process. Accordingly, a driving electrode including any one of thepixel electrode and the common electrode may expose the transparentconductive film included in them upon the second or third mask process.The lower array substrate may be formed by the three-round mask processin this manner, so that it becomes possible to simplify its structureand its manufacturing process, thereby reducing manufacturing costs andimproving production yield. Furthermore, the transparent conductive filmincluded in the pad may be exposed by a pad opening process after thejoining of the substrates, or the printing of the alignment film,thereby preventing corrosion of the pad electrode.

It will be apparent to those skilled in the art that variousmodifications and variations can be made in the LCD panel device andmethod of fabricating an LCD panel device of the present inventionwithout departing from the spirit or scope of the invention. Thus, it isintended that the present invention cover the modifications andvariations of this invention provided they come within the scope of theappended claims and their equivalents.

What is claimed is:
 1. A method of fabricating a liquid crystal displaypanel device, the method comprising: providing a lower array substratecomprising: a gate line provided on a substrate, wherein the gate lineis formed of a double-layer structure including a transparent conductivefilm and a gate metal film sequentially; a data line provided on asubstrate intersecting the gate line to define a pixel area; a thin filmtransistor provided at the intersection between the gate line and thedata line, the thin film transistor having a semiconductor pattern; aprotective film for protecting the thin film transistor; a pixelelectrode directly formed on the pixel area of the substrate, the pixelelectrode being directly connected to a drain electrode of the thin filmtransistor, and being formed of the transparent conductive film; a gatepad connected to the gate line and formed from the transparentconductive film; and a data pad connected to the data line and formedfrom the transparent conductive film; providing a color filter arraysubstrate opposed to the thin film transistor array substrate; joiningthe thin film transistor array substrate with the color filter arraysubstrate to expose a pad area including the gate pad and the data pad;and exposing the transparent conductive film at the pad area using thecolor filter array substrate as a mask, wherein the pixel electrode, thegate pad and the data pad include the same transparent conductive film,wherein the semiconductor pattern forms a channel between a sourceelectrode and the drain electrode and include an active layer partiallyoverlapping with a gate electrode of the thin film transistor, whereinthe semiconductor pattern includes an ohmic contact layer for makingohmic contact with the data line, the source electrode, and the drainelectrode, wherein each of the gate pad and the data pad is formed of asingle layer that is identical with the transparent conductive film ofthe pixel electrode, and wherein the gate pad and the data pad aredirectly contacted with the substrate.
 2. The method according to claim1, wherein the step of providing the lower array substrate includes:forming gate patterns having the gate line, the gate electrode, the gatepad, and the data pad including the transparent conductive film and thepixel electrode on the substrate; forming a semiconductor pattern and agate insulating pattern on the substrate provided with the gate patternsand the pixel electrode and exposing the transparent conductive filmsincluded in the data pad, the gate pad, and the pixel electrode; forminga data pattern including the data line, a source electrode, and a drainelectrode on the substrate provided with the semiconductor pattern andthe gate insulating pattern; and forming a protective film on thesubstrate provided with the data pattern.
 3. The method according toclaim 1, wherein the step of providing the lower array substrateincludes: forming gate patterns having the gate line, the gateelectrode, the gate pad, the common line, the common electrode, thecommon pad, and the data pad including the transparent conductive filmand the pixel electrode on the substrate; forming a semiconductorpattern and a gate insulating pattern on the substrate provided with thegate patterns and the pixel electrode; forming a data pattern includingthe data line, a source electrode, and a drain electrode on thesubstrate provided with the semiconductor pattern and the gateinsulating pattern and exposing the transparent conductive filmsincluded in the data pad, the gate pad, the common pad, the commonelectrode, and the pixel electrode; and forming a protective film on thesubstrate provided with the data pattern.
 4. The method according toclaim 1, wherein the step of providing the color filter array substrateincludes: providing a common electrode for creating a vertical electricfield with the pixel electrode.
 5. The method according to claim 1,wherein the step of exposing the transparent conductive film includes:dry etching the protective film by an atmosphere plasma using the colorfilter array substrate as a mask.
 6. The method according to claim 1,wherein the step of exposing the transparent conductive film includes:dry etching the protective film by a normal-pressure plasma using thecolor filter array substrate as a mask.
 7. The method according to claim1, wherein the step of exposing the transparent conductive filmincludes: wet etching the protective film exposed by the color filterarray substrate by liquid crystal cells made by a joining of the colorfilter array substrate with the thin film transistor array substrate.